The present invention relates to an interrupt controller, an ASIC, and electronic equipment.
Embedded type CPUs (microprocessors) have recently been placed in the limelight. The objective of an embedded type CPU is that is should be incorporated as an ASIC core. In other words, the user uses such a CPU as an ASIC core, and components other than the CPU can be designed by the user, using gate arrays or the like.
One type of CPU that is becoming well known as the embedded type CPU is the ARM (Advanced RISC Machines) produced by ARM Ltd. This ARM is an inexpensive RISC type of CPU that is small, has a low power consumption, but enables high-speed throughput. It is expected that ASICs using such ARMs as cores will be suitable for incorporation into electronic equipment such as portable telephones and GSM devices.
However, various technical problems relating to interrupt processing have been identified with these ARM devices, as described below.
The standard operation of an ARM during interrupt processing is shown in FIG. 1, by way of example.
(A) When one of interrupt requests IR0 to IR31 is input to an interrupt controller 610 from the outside, an interrupt factor register 612 within the interrupt controller 610 saves the interrupt factor. The interrupt controller 610 generates an interrupt request IRQ (a normal-level interrupt request) to inform a CPU (ARM) 600 that there is an external interrupt request.
(B) On receiving the IRQ, the CPU 600 reads an interrupt vector 622 that is stored at a vector address (00000018H) in a memory 620, as shown at A1 in FIG. 1. An interrupt processing routine (interrupt handler) 624 having a start address specified by the interrupt vector 622 is activated, as shown at A2.
(C) The activated interrupt processing routine 624 checks the interrupt factor that is stored in the interrupt factor register 612. Subsequent processing depends on this interrupt factor.
In this ARM device, only one vector address (storage address for an interrupt vector) can be specified (00000018H). The hardware can therefore branch only to the interrupt processing routine 624 at one location, so that branching to interrupt processing routines at a plurality of locations can only be done by software means within the interrupt processing routine 624.
Japanese Patent Application Laid-Open No. 63-165929 discloses a conventional technique for incorporating an interrupt vector table into the interrupt controller. When an external interrupt is generated with this conventional technique, the interrupt controller issues an interrupt request to inform the CPU. When the interrupt controller receives an ACK signal from the CPU, it outputs an interrupt vector that is stored in an interrupt vector table to the CPU through a bus.
Since the interrupt vector table is provided within the interrupt controller with this conventional technique, however, various problems occur such as an increase in the size of the hardware of the interrupt controller and an increase in cost. There are also further problems, such as increasing complexity of memory control and bus control.
The present invention was devised in the light of the above described technical problems, with the objective of providing an interrupt controller, ASIC, and electronic equipment that make it possible to branch directly to interrupt processing routines at a plurality of locations.
The present invention was devised to solve the above-described technical problems, by providing an interrupt controller for controlling interrupt, comprising:
means for generating an interrupt request to a processor when an external interrupt request is received;
means for trapping an address from the processor, and for determining whether or not the processor which receives the interrupt request has executed a read instruction for an interrupt vector, based on the trapped address; and
means for generating a vector table address corresponding to a factor of the external interrupt request, with respect to a memory storing an interrupt vector table, when it is determined that the read instruction for the interrupt vector has been executed.
This aspect of the present invention generates an interrupt request to a processor when an external interrupt request is received. On reception of this interrupt request, the processor executes a read instruction for an interrupt vector (the start address of an interrupt processing routine). In such a case, the interrupt controller of the present invention traps an address from the processor then determines whether or not the read instruction for the interrupt vector has been executed, based on the thus-trapped address. When it determines that the instruction has been executed, it then outputs a vector table address (the storage address of an interrupt vector table) corresponding to the factor of the received external interrupt request, to a memory. This causes the output of the interrupt vector that corresponds to the factor of the external interrupt request, from the memory that stores the interrupt vector table. This configuration of the present invention makes it possible to branch directly to interrupt processing routines at a plurality of locations, even when the processor itself can only specify one vector address for the interrupt vector. As a result, it becomes possible to increase the speed of processing and simplify the programming.
In the present invention, the processor and the memory may be connected to a higher-performance first bus and the interrupt controller may be connected to a lower-performance second bus. The interrupt vector table in accordance with the present invention is stored in a memory, not in the interrupt controller. It is therefore possible to read the interrupt vector table from a memory over the higher-performance first bus, even if the interrupt controller is connected to the lower-performance second bus. As a result, the speed of the interrupt processing can be increased, even though the hardware of the interrupt controller can be made smaller.
The interrupt controller of the present invention may generate an address switching signal output to a selector which selects and outputs one of the address from the processor and the vector table address from the interrupt controller. This configuration makes it possible to minimize signal delays for addresses from the processor during normal operation.
The present invention may further comprise a base register which stores a base address of the vector table address, and the interrupt controller may generate the vector table address based on the factor of the external interrupt request and the base address from the base register. This configuration makes it possible to make the device more convenient to the user, by enabling the storage of a series of interrupt vectors at addresses within a memory as desired by the user.
The present invention may comprise a first mode and a second mode which are switchable therebetween, processing that traps the address from the processor and generates the vector table address being enabled in the first mode and being disabled in the second mode. This makes it possible to respond to demands from users who wish for operation in a first mode in which the vectortable address is generated and also to demands from users who wish for operation in a standard second mode.
An ASIC in accordance with the present invention comprises one of the above described interrupt controllers; the processor which executes instructions; and the memory which stores at least the interrupt vector table. This configuration makes it possible to provide an ASIC that responds demands by various levels of users.
Electronic equipment in accordance with the present invention comprises the above described ASIC; input means for inputting data; and output means which outputs at least one of an image and a sound under a control of the ASIC. This configuration makes it possible to branch directly and immediately to an interrupt processing routine that corresponds to any of a plurality of operations done by using the input means, by way of example. This simplifies the program for operating the electronic equipment and also increases the speed of processing.